The present invention relates to a process for fabricating printed circuit boards, sometimes referred to as printed wiring boards, and, more particularly, to a "semi-additive" process for producing circuit boards and apparatus for practicing that process which uses steps of addition and subtraction of copper.
Printed circuit boards are known electronic component structures which contain copper strips or paths arranged in a pattern on a relatively flat electrically insulative structure or base. The copper strips form current-conducting paths, the electric wiring, by means of which other electrical components thereafter mounted on the board may receive or pass electrical current to other electrical components, similarly mounted, or from a power source. These circuit boards are notoriously old and well-known, having achieved wide application in all kinds of electronic devices, including radios, televisions, and computers, to name a few, and various types and processes provide pertinent background to the present invention.
One circuit board structure is referred to as a two-sided plated through-hole board. The board contains electrical conductors on its front and back surfaces, and at least some of those conductors on opposite sides are electrically inter-connected by means of the plated "through-hole" connections. The through-hole is a hole formed through the board between intercepting conductors on the opposite board sides and the hole wall is plated with metal electrically connecting the two conductors. A number of these circuit boards may be laminated or bonded together to form what is known as a multilayer printed circuit board, and in such multilayer circuit board aligned through-holes may form electrical connections to different circuit boards in the bonded stack. A less complex printed circuit board is a single-sided plated through-hole circuit board in which a through-hole is drilled through the board and plated with metal even though a conductor circuit pattern appears on only one board surface. This configuration is often desired because it assists in soldering of components to the board and that advantage justifies the additional cost to some users over single-sided boards having unplated component mounting holes.
Prior art manufacturing processes are characterized as subtractive or as additive processes. Still others, as the present invention, are characterized as semi-additive. An example of a subtractive process for a single-sided board is one in which a copper foil, usually relatively thick, is applied to an insulating base substrate, desired mounting holes are formed therein, and an etch-resist material is applied or formed over the copper layer in the positive image of the desired circuit configuration. The board is immersed in a copper etchant that removes the copper from the areas unprotected by the resist. Thereafter, the etch-resist material is removed to expose the protected copper, leaving the desired electrical circuit configuration. Because the copper layer is relatively thick, a strong etchant and considerable time is required to accomplish the fabrication and much copper is obviously wasted in being etched away.
Where plated through-holes are required, the foregoing subtractive process is modified in an "additive" way by forming the holes and then electrolessly plating over the copper covered laminate to coat the thick copper layer and the hole walls. An etch-resist is then applied over the electroless copper surface in the negative image of the desired pattern and copper is electrolytically applied to the desired thickness. Then a dissimilar metal-resist pattern is applied over the portions of the copper surface to be retained, typically by electrolytic plating of a nickel metal or a solder metal (tin-lead), to cover the plated hole walls as well, and in the subsequent step of etching, generally only the undesired copper is removed. It is apparent in this essentially subtractive process, even greater amounts of copper must be etched away, including some of that expensive electroless copper deposited over the copper layer. Moreover, there is greater waste, hence expense, in that copper is built up on those areas of the laminated copper layer where it was not needed and expensive metal-resist is required over large areas.
A purely additive process is one where an insulating base substrate is masked in the negative image of a desired conductor configuration and treated and then receives a deposit of copper on the substrate surfaces only in those areas where the desired circuit configuration is desired, usually accomplished in part by immersion in an electroless copper bath.
The relative advantage and disadvantage of each of these processes as industrially applied is generally known: The subtractive process producing circuit boards in which the copper is firmly attached to the insulating base with the greatest "peel" strength, the measure of adherence of the bond, whereas with the additive processes presently available to industry, the desired levels of peel strength between the copper and insulating base substrate have not, in my opinion, equaled that available with the subtractive process on a production basis or at reasonable cost. Conversely, the subtractive process involves extensive etching of thick copper material with much waste of copper and long etching requirements, particularly in those structures as described requiring plated through-holes, and in times of rising copper prices this is a significant factor for the consumers. Moreover, due to a phenomenon known as "undercutting" in the subtractive process, in which the etchant etches sideways into the sides of the resist covered copper areas during etching in addition to etching down into the uncovered copper areas the desired direction, the width or "fineness" of a conductor line on a printed circuit board made by the subtractive process is necessarily limited, whereas finer conductor lines, those of ten mils or less in width, may be made using a purely additive process. This is significant since the line width serves as a limit on the density of conductor circuits which can be placed on the circuit board. In addition, undercutting reduces the area over which the plated line contacts the base and thus reduces the peel strength, which is somewhat proportional to the contact area.
Another consideration is that the subtractive process utilizing electroplating techniques produces a ductile copper deposit which withstands temperature shocks induced by soldering and/or temperature extremes without cracking. Additive processes have been both technically and economically limited in this regard: The quality of copper deposited appears less consistent and does not routinely withstand temperature shock testing over a period of time.
By way of specific example, certain patent literature has been made known to me which describe additive and subtractive processes and parts and intermediate processes, many of which may never have been industrially adopted but which are considered prior art and the reader's attention is invited to these as further background:
U.S. Pat. No. 3,930,963, issued Jan. 6, 1976, to Polichette et al; PA0 U.S. Pat. No. 3,625,758, issued Dec. 7, 1971, to Stahl et al; PA0 U.S. Pat. No. 3,956,041, issued May 11, 1976, to Polichette et al; PA0 U.S. Pat. No. 3,854,973, issued Dec. 17, 1974, to Mersereau et al; PA0 U.S. Pat. No. 3,694,250, issued Sept. 26, 1972, to Grunwald et al; PA0 U.S. Pat. No. 3,628,999, issued Dec. 21, 1971, to Schneble et al; PA0 U.S. Pat. No. 3,874,897, issued Apr. 1, 1975, to Fadgen et al; PA0 U.S. Pat. No. 3,960,573, issued June 1, 1976, to Zeblisky et al; PA0 U.S. Pat. No. 3,635,758, issued Jan. 18, 1972, to Schneble et al; PA0 U.S. Pat. No. 3,615,736, issued Oct. 26, 1971, to Stone et al; PA0 U.S. Pat. No. 3,865,623, issued Feb. 11, 1975, to Allen et al;
the disclosures of which are referred to and incorporated herein by reference for the processes, the chemical ingredients and the equivalents they disclose.
Considering the large number of concerns which produce printed circuit boards on a low and on a high volume basis and the ready availability of circuit boards at reasonable cost and acceptable quality, as well as the numerous process variations available to the industry evidenced by the afore-cited prior art patents, the reader recognizes that the art of manufacturing printed circuit boards is fairly well developed and an almost limitless variety of possible alternative and substituent ingredients in these processes exist at least as proposals, as is made more apparent later in this specification. With the great variety of technology one skilled in the art conceivably could experiment with each possible permutation of ingredients suggested or proposed by the prior art in an attempt to define ingredients, parameters and ranges as an attempt to define an industrially acceptable high volume printed circuit board of comparable or better quality than those available, and yet, though quality is achieved, the person may ultimately discover that the processes taught by the prior art, uncovered and evaluated through great effort, is uneconomical on a high volume basis in competition with other known printed circuit board manufacturing processes or produces a slight increase in quality but at an unacceptable increase in cost and so as to render the product of his efforts unsaleable. In this respect, the reader appreciates the scientific work of those skilled in this field, particularly in additive processes, whose obvious curiosity and desire to enhance the quality and use of circuit boards has resulted in many achievements in ingredient chemicals and treatments used in the manufacture of printed circuit boards heretofore, including those without which the present invention would not be possible. However, those additive processes which have been made industrially available, though recognized as an apparent accomplishment, does not, in the opinion of applicant, produce circuit boards that are competitive with the subtractive process on a cost and quality basis, the first serving to limit the extent of the market for circuit boards produced in that manner and the latter serving to reduce yields and hence increase costs. Hence, the availability of circuit boards containing high density circuits with very thin lines sufficiently bonded to the board is based upon the payment of a substantial premium and hence is likely to be limited to a lower volume market than desired as a natural consequence of the inherently higher price.
By way of more specific background to the present invention, patent U.S. Pat. No. 3,930,963 to Polichette et al discloses an additive process for manufacturing printed circuit board which commences with an epoxy glass laminate base material which is put through a series of chemical treatment steps, including treatment in an absorber, drying, rinsing, punching holes, pre-activation, draining, oxidizing, and reducing to render the board surface microporous. That is followed by removing excess agents, poisoning, and applying a layer of a reducible metal compound, masking and exposing the compound to ultraviolet light, and rinsing away the unexposed salts to leave a metal "positive" image of the desired copper conductor configuration. This is followed by electroless plating and additional plating, such as electroplating to a thickness of 0.001 to 0.003 inches.
In an alternative treatment therein described, the insulative base material is passed under a "curtain coater" and covered with an oxidizable adhesive layer which is then dried at a temperature of 160 degrees for about one hour, and the "through-holes" are punched out of the base. The base is then immersed in an oxidizer to produce a microporous surface in the adhesive layer. This appears similar to that described in the patent cited in the paragraph which follows. The board is then rinsed, neutralized in an acidic sodium bisulfate solution followed by the application of the poison layer and then the board is coated with the radiant energy sensitive reducible metal salt layer. The additional steps for building up the thickness of the copper thereafter is followed.
Another patent, U.S. Pat. No. 3,625,758, issued Dec. 7, 1971 to Stahl et al, owned by Photocircuits Division of Kollmorgan Company, describes a number of semi-additive processes for making two-sided printed circuit boards containing plated through-holes. In one, which Stahl refers to as prior art, an insulating base has a thick electrolytic copper foil laminated to the surfaces of the substrate, followed by drilling of the through-holes, activation of the substrate with silver nitrate or tin and noble metal ions activating solution and then depositing electroless copper on top of the copper foil and on the walls of the formed holes, accomplished by immersion in an electroless copper plating solution. Thereafter, a first protective coating is applied to the formed board in the negative image of the desired conductor configuration leaving exposed those regions of the electroless copper corresponding to the desired conductor configuration. A copper layer is then electroplated on top of the exposed electroless copper portions, including the hole walls. Thereafter the treated substrate is electroplated with an etch-resistant second protective coating, such as silver, tin, lead or gold, to cover the surfaces of the electroplated copper applied in the previous step. The first protective layer is removed and the structure is immersed for a time in a copper etchant which removes the uncovered electroless copper and the underlying thick copper foil, the second protective coating protecting, generally, the other underlying copper portions from the etchant. The copper underlying the second protective coating forms the desired conductor configuration on the circuit board. The described method is characterized in the text of the patent as expensive with respect to the amounts of copper to be etched and to the large amount of equipment required to perform the process. Further, the etch-resistant second metal protective coating and its application adds to cost.
The U.S. Pat. No. 3,625,758 Stahl patent describes another semi-additive process by way of improvement which is relevant to the instant invention, in which an insulative base substrate material, such as phenolic paper board or the like, is brushed or sanded to clean and roughen the surface and treated with suitable activating solutions for the electroless deposition of copper. Thereafter the entire surface is provided with a thin layer of electroless copper which covers all the surfaces and the hole walls to a thickness, which applicant speculates upon as between 25 to 35 microns. Thereafter, a coating is applied to the surface of the board in the negative image of the desired conductor configuration for the circuit board to be formed leaving exposed the electroless copper in the desired locations. Thereafter the structure is electroplated with copper to build up the thickness of the copper in the desired area. The protective layer is then removed, such as with a stripping solution, and the uncovered electroless copper is etched away, although such etching is not particularly described, leaving the desired conductor configuration. Stahl notes that the method avoids the application of unnecessary copper but has a serious drawback of lack of sufficient bond between the surface of the base material and the copper conductors, which applicant concludes as teaching the process to be unacceptable, and notes proposals to make the previously defined process acceptable, eliminating that defect with additional process steps by equipping the surface of the insulating material with an adhesive and subjecting the completed board to a heat hardening and pressing process requiring expense in manufacturing equipment, processing, as well as imposing greater demands upon manufacturing personnel. Stahl notes that it is frequently necessary to add an electroplated protective coating on top of the original electroless copper coating unless extreme cost increasing care is to be taken in handling the semi-finished product, all of which leads to complication and higher price of production for the finished product which have rendered that process almost noncompetitive with that produced by the copper foil etching methods previously described in Stahl. To remedy that, Stahl proposes an improved structure for the base material and then illustrates such product in various semi-additive processes to achieve sufficient bond between the copper conductors and the board at an asserted competitive manufacturing cost.
In this, a suitable base, such as phenolic paper, epoxide paper, epoxy fiberglass laminates and the like, is provided with a layer which firmly adheres and which can be hardened by heat and contains at least one substance which is uniformly distributed in the layer and belongs to the group of modified rubbers or synthetic rubbers and can be oxidized and degraded by suitable oxidizing agents to form a microporous surface suitable for the deposition of electroless copper. The thickness of this coating is noted as 10 to 30 microns.
In one process, Example V in Stahl, a prepared base material, according to his Example IV, is treated in an acidic stannous chloride solution, an acidic palladium chloride solution and immersed in an alkaline electroless copper plating solution to build a thin copper foil of between 3 and 6 microns thickness over a period of 45 minutes to one hour and a half. From that, a solvent strippable ink mask is applied in the negative image of the desired circuit pattern and immersed in an electroless copper plating bath until the exposed copper is built up to desired thickness. The mask is removed in a "customary manner" and the underlying foil is removed by brief treatment in ammonium persulfate or other suitable solvent. This infers that the alkaline copper etchant as a consequence must remove some of the conductor as well at the same etching rate, although not clearly stated, a fact most relevant to the process of my invention. In another process, Example VI, using the improved base structure of Example V having electroless copper plating layer of about 5 microns thickness on the substrate, a protective solvent removable ink mask in the negative image of the desired conductor configuration is applied, the board is then cleaned in an alkaline solution, rinsed, reactivated in an acid solution and then immersed in an electroless copper bath to deposit additional electroless copper and build up the conductors to a thickness of 35 microns in a period of fifteen hours. This is followed by dissolving the mask. Although not clear from the patent, it is assumed that this is followed by removal of the exposed electroless copper in an etchant, ammonium persulfate, such as given in the earlier example, which necessarily etches the conductors also.
Commencing with the masked board as derived in his Example VI, in an Example VII an alkaline (i.e. caustic) copper electroplating solution, suitably pyrophosphate-copper, is used to build up the thickness of the exposed copper in the areas unprotected by the ink mask, to 35 microns in about 45 minutes, as an alternative to the electroless copper. In this example it is stated that the mask is removed and that the thin base copper exposed by removal of the mask is dissolved, although particular details are not given. It is possible to infer that the method exposes the electroplated copper also to the etchant, much like in my invention. Stahl also notes that in his processes he has found it particularly advantageous to use masking inks which are dissolved or stripped in an alkaline solution in connection with electroless copper plating to build up the conductors which in the previous examples were all alkaline based electroless copper plating solutions and which one would believe would dissolve or strip the mask. This prior art proposal of Stahl thus leaves some ambiguities. However, with all the ambiguities the Stahl disclosure is most pertinent to the invention.
One recognizes from the foregoing examples of Stahl that copper electroplating is more rapid than electroless copper plating. Hence, if time is equated with expense, electroplating is an obvious favorite. Despite the advantages asserted in the Stahl patent, I have not learned of any industrially available process which uses the process of Example VII and the like to produce acceptable quality circuit boards at competitive prices and know only of the efforts of the patent owner to promote practice of fully additive processes, which in my opinion suffers from the high cost and lower quality inherent in such processes, using the laminate treatment described in the patent, and assume that the work forming pertinent background to my discovery was regarded by the patent owner as less attractive than the additive processes which the patent owner promotes.
The Mersereau patent, U.S. Pat. No. 3,854,973, granted Dec. 17, 1974, owned by MacDermid Company, describes many printed circuit board manufacturing techniques. One of these involves initially immersing the base substrate in an organic solvent, for example one which includes dimethyl sulfoxide, followed by immersion in an appropriate chromic sulfuric oxidizing solution and thereafter catalizing of the board with an appropriate electroless plating catalyst. Thereafter it is suggested that the board be subjected to direct electroless plating by applying a thin initial deposit of conductive metal over the entire surface of the board followed by the application of a plating resist or mask and its development to form a suitable negative image of the desired circuit pattern. This is followed by further electrolytic plating or electroless deposition of conductor metal to build up the thickness of the conductor configuration. Then a different protective metal etch "resist" layer, such as nickel or tin-lead, is deposited over the conductors. The plating resist is removed, exposing the underlying electrolessly deposited copper followed by immersing the board in an etching solution to remove the initial thin continuous coating of the conductive metal. Thereafter the protective metal coating may be removed from over the copper or, I assume, alternatively left in place. The protective metal resist obviously can be equated with an expense. An alternative process described in the patent is to form a positive resist image directly on the bare board and to electrolessly deposit copper on the exposed portions up to the desired thickness. This appears as a purely additive process. In either procedure, U.S. Pat. No. 3,854,973 recommends that either before or after plating, the base substrate is baked to promote effective bonding between the conductor and the base substrate.
One variation which may seem obvious is to use the adhesive layer described in the cited U.S. Pat. No. 3625,758 to Stahl or an equivalent substance as a substitute for initial treatment in the process described in the cited U.S. Pat. No. 3854,973 where a coverall copper layer is electrolessly deposited on the board, but in fact the mating of the two different processes to produce an industrially acceptable printed circuit board, as is apparent to one skilled in the art, is intrinsically difficult to accomplish and, in my opinion, is not obvious. And even if successful, that process includes the addition of a metal resist as therein described.
Against the foregoing background of suggested processes of additive or semi-additive types with which the present invention is concerned and the different specific examples of treatment, applicant was not presented with any complete industrial additive or semi-additive process for producing circuit boards that produce the combination of peel strength and cost competitiveness with boards produced by industrially available subtractive manufacturing processes.
The cost of producing printed circuit boards of acceptable quality depends upon many factors, including the cost of materials and chemicals, the cost of equipment, and the cost of labor and handling, as well as the ultimate process "yield", the portion of acceptable quality boards from all the boards emerging from the treatment process. In connection with process yield is the permissibility of salvaging those circuit boards produced which do not meet the quality standards.
Circuit boards made by the subtractive process are not effectively "salvageable". This is, if after processing the resultant board is defective and no manual repairs are permitted, it is virtually impossible economically to etch off the thick copper and apply a new copper layer to reprocess the board. Boards produced by the subtractive process rely upon the strong bond between the copper layer and the circuit board as applied by the laminating company that originally manufactured the board and copper foil combination and this is done on a high volume basis to be economical.
In respect of the additive processes I have found that at least one of the processes is not salvageable. This is a process in which an aluminum sheet is laminated to a circuit board and oxidized to create a surface roughness. The aluminum layer is then chemically stripped from the board so as to leave the rough surface for electroless copper plating and the like. However, in attempting to salvage circuit boards undergoing that process, after all the copper is stripped from the board, for unknown reasons, it appears impossible to effectively replate copper on the base material. However, that may not be the case with all additive processes since I have not had time or interest to experiment with all of them. For example, one process relies upon a surface catalyst which is activated by treatment of the base material in a chrome solution. In that process, after all the plated copper is stripped from the board to be salvaged, the teaching is that the board is reintroduced into the chrome solution and that solution replenishes the surface catalyst. However, I have not actually practiced such an operation and I believe the process overall to suffer the same disadvantages of additive processes hereinbefore described by way of background to the present invention.
The translation of the prior art knowledge into an improved commercially viable industrial application has thus been wanting, in applicant's opinion.